@INPROCEEDINGS{Wu2011,
author={Xiaoxia Wu and Wei Zhao and Chandra Nimmagadda and Durodami Lisk and Mark Nakamoto and Sam Gu and Riko Radojcic and Matt Nowak and Yuan Xie},
booktitle={TVLSI},
title={{Electrical Characterization for Inter-tier Connections and Timing Analysis for 3D ICs}},
year={2011},
}

@INPROCEEDINGS{Jing_3D, 
author={Jing Xie and Jishen Zhao and Xiangyu Dong and Yuan Xie}, 
booktitle={APCCAS},
title={{Architectural benefits and design challenges for three-dimensional integrated circuits}}, 
year={2010}, 
pages={540 -543}, 
}

@Article{Xie_3D, 
author={Yuan Xie and Gabe Loh and Bryan Black and Kerry Bernstein}, 
booktitle={ACM Journal of Emerging Technologies for Computer Systems},
title={Design Space Exploration for 3D Architecture}, 
year={2006},
volume={2}, 
number={2},
pages={65-103}, 
} 

@Article{Xie_3D1, 
author={Yuan Xie and Gabe Loh and Bryan Black}, 
booktitle={IEEE Micro},
title={Processor Design in Three-dimensional Die-Stacking Technologies}, 
year={2007},
volume={27}, 
number={3},
pages={31-48}, 
} 

@INPROCEEDINGS{3D_wireless_test, 
author={Marinissen, E.J. and Dae Young Lee and Hayes, J.P. and others}, 
booktitle={DATE},
title={{Contactless testing: Possibility or pipe-dream?}}, 
year={2009}, 
pages={676 -681},}

@INPROCEEDINGS{Jing:probe,
AUTHOR = "William R. Mann and Frederick L. Taber and Philip W. Seitzer and Jerry J. Broz",
TITLE = {{The Leading Edge of Production Wafer Probe Test Technology.}},
booktitle = {ITC},
PAGES = {1168-1195},
YEAR = {2004}  }

@book{Jing:testbook,
  title={{Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits}},
  author={Bushnell, M.L. and Agrawal, V.D.},
  isbn={9780792379911},
  lccn={00046212},
  series={Frontiers in electronic testing},
  url={http://books.google.com/books?id=CgnLg99GumMC},
  year={2000},
  publisher={Kluwer Academic}
}

@ARTICLE{Jing:IMEC, 
author={Van der Plas, G. and Limaye, P. and Loi, I. and others}, 
journal={JSSCC}, 
title={{Design Issues and Considerations for Low-Cost 3-D TSV IC Technology}}, 
year={2011}, 
volume={46}, 
number={1}, 
pages={293 -307}, 
}

@INPROCEEDINGS{Jing:redundancy, 
author={Ang-Chih Hsieh and TingTing Hwang and Ming-Tung Chang and others}, 
booktitle={DATE}, 
title={{TSV redundancy: Architecture and design issues in 3D IC}}, 
year={2010}, 
}

@inproceedings{Jing:cost,
 author = {Dong, Xiangyu and Xie, Yuan},
 title = {{System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs)}},
 booktitle = {ASP-DAC},
 year = {2009},
}

@article {Jing:TSV,
   author = {Lou, Yi and Yan, Zhuo and Zhang, Fan and Franzon, Paul},
   affiliation = {Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC, USA},
   title = {{Comparing Through-Silicon-Via (TSV) Void/Pinhole Defect Self-Test Methods}},
   journal = {Journal of Electronic Testing},
   publisher = {Springer Netherlands},
   issn = {0923-8174},
   year = {2011},
   keyword = {Computer Science},
   pages = {1-12},
}

@INPROCEEDINGS{Jing:Xiaoxia, 
author={Xiaoxia Wu and Yibo Chen and Chakrabarty, K. and Yuan Xie}, 
booktitle={ICCD}, 
title={{Test-access mechanism optimization for core-based three-dimensional SOCs}}, 
year={2008}, 
pages={212 -218}, 
}

@INPROCEEDINGS{TSVstress, 
author={Moongon Jung and Mitra, J. and Pan, D.Z. and Sung Kyu Lim}, 
booktitle={DAC}, 
title={{TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC}}, 
year={2011}, 
pages={188 -193},}

@INPROCEEDINGS{TSVmobility, 
author={Chaabouni, H. and Rousseau, M. and Leduc, P. and others}, 
booktitle={IEDM}, 
title={{Investigation on TSV impact on 65nm CMOS devices and circuits}}, 
year={2010},  
pages={35.1.1 -35.1.4}, 
}

@misc{tezzaron,
howpublished = {\url{http://www.tezzaron.com/TezzaronBest3DIC.html}},
year={2011},
title={{Tezzaron: The very best in 3D-IC}},
author={Tezzaron},
}

@INPROCEEDINGS{tsvmodel, 
author={Cadix, L. and Rousseau, M. and Fuchs, C. and others}, 
booktitle={IITC}, 
title={{Integration and frequency dependent electrical modeling of Through Silicon Vias (TSV) for high density 3DICs}}, 
year={2010},  
pages={1 -3}, 
}

@INPROCEEDINGS{BIST, 
author={Yu-Jen Huang and Jin-Fu Li and Ji-Jan Chen and others}, 
booktitle={VTS}, 
title={{A built-in self-test scheme for the post-bond test of TSVs in 3D ICs}}, 
year={2011}, 
pages={20 -25}, 
}

@INPROCEEDINGS{KGS, 
author={Marinissen, E.J. and Zorian, Y.}, 
booktitle={ITC}, 
title={{Testing 3D chips containing through-silicon vias}}, 
year={2009}, 
pages={1 -11}, 
}
